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INTEGRATED CIRCUITS
DATA SHEET
74LVC00A Quad 2-input NAND gate
Product specification Supersedes data of 1998 Apr 28 2002 Mar 05
Philips Semiconductors
Product specification
Quad 2-input NAND gate
FEATURES * 5 V tolerant inputs for interfacing with 5 V logic * Wide supply voltage range from 1.2 to 3.6 V * CMOS low power consumption * Direct interface with TTL levels * Inputs accept voltages up to 5.5 V * Complies with JEDEC standard no. 8-1A * Specified from -40 to +85 C and from -40 to +125 C. DESCRIPTION
74LVC00A
The 74LVC00A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The 74LVC00A provides the 2-input NAND function.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION PACKAGES TYPE NUMBER TEMPERATURE RANGE 74LVC00AD 74LVC00ADB 74LVC00APW -40 to +125 C -40 to +125 C -40 to +125 C PINS 14 14 14 PACKAGE SO SSOP TSSOP MATERIAL plastic plastic plastic CODE SOT108-1 SOT337-1 SOT402-1 PARAMETER propagation delay nA, nB to nY input capacitance power dissipation capacitance per gate CONDITIONS CL = 50 pF; VCC = 3.3 V TYPICAL 2.1 4.0 VCC = 3.3 V; notes 1 and 2 15 ns pF pF UNIT
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
FUNCTION TABLE See note 1. INPUTS nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. PINNING PIN 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 1A to 4A 1B to 4B 1Y to 4Y GND VCC SYMBOL data input data input data output ground (0 V) supply voltage nB L H L H
74LVC00A
OUTPUTS nY H H H L
DESCRIPTION
handbook, halfpage
handbook, halfpage
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
MNA210
14 VCC 13 4B 12 4A
1 2 4 5 9 10 12 13
1A 1B 2A 2B 3A 3B 4A 4B
1Y
3
2Y
6
00
11 4Y 10 3B 9 8 3A 3Y
3Y
8
4Y
11
MNA212
Fig.1 Pin configuration.
Fig.2 Logic symbol.
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
handbook, halfpage
1 2
&
3
4 5
&
6
handbook, halfpage
A Y
9 10
&
8
B
MNA211
12 13
&
11
MNA246
Fig.3 Logic symbol (IEEE/IEC).
Fig.4 Logic diagram (one gate).
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage CONDITIONS for maximum speed performance for low-voltage applications VI VO Tamb tr,tf input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V MIN. 2.7 1.2 0 0 -40 0 0 MAX. 3.6 3.6 5.5 VCC +125 20 10 V V V V C ns/V ns/V UNIT
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg Ptot PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation per package SO package SSOP and TSSOP packages Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. above 70 C derate linearly with 8 mW/K above 60 C derate linearly with 5.5 mW/K - - 500 500 mW mW VI < 0 note 1 VO > VCC or VO < 0 note 1 VO = 0 to VCC CONDITIONS - -0.5 - -0.5 - - -65 MIN. -0.5 MAX. +6.5 -50 +6.5 50 VCC + 0.5 50 100 +150 V mA V mA V mA mA C UNIT
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level VI = VIH or VIL output voltage IO = -100 A IO = -12 mA IO = -18 mA IO = -24 mA VOL LOW-level VI = VIH or VIL output voltage IO = 100 A IO = 12 mA IO = 24 mA II ICC input leakage current quiescent supply current additional quiescent supply current per input pin VCC (V) 1.2 2.7 to 3.6 1.2 2.7 to 3.6 2.7 to 3.6 2.7 3.0 3.0 2.7 to 3.6 2.7 3.0 MIN. VCC 2.0 - - VCC - 0.2 VCC - 0.5 VCC - 0.6 VCC - 0.8 - - - - - -40 to +85 TYP.(1) - - - - - - - - - - - 0.1 0.1 MAX. - - GND 0.8 - - - - 0.2 0.4 0.55 5 10 2.0 - - Tamb (C)
74LVC00A
-40 to +125 MIN. VCC MAX. - - GND 0.8 - - - - 0.3 0.6 0.8 20 40
UNIT
V V V V V V V V V V V A A
VCC - 0.3 VCC - 0.65 VCC - 0.75 VCC - 1 - - - - -
VI = 5.5 V or GND 3.6 VI = VCC or GND; IO = 0 VI =VCC - 0.6V; IO = 0 3.6
ICC
2.7 to 3.6
-
5
500
-
5000
A
Note 1. All typical values are at VCC = 3.3 V and Tamb = 25 C.
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns. Tamb (C) SYMBOL PARAMETER WAVEFORMS -40 to +85 MIN. TYP.(1) MAX. VCC = 1.2 V tPHL/tPLH VCC = 2.7 V tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 1.5 2.4 5.1 1.5 propagation delay nA, nB to nY see Figs 5 and 6 - 12 - -
74LVC00A
-40 to +125 MIN. MAX. -
UNIT
ns
6.5
ns
VCC = 3.0 to 3.6 V tPHL/tPLH tsk(0) Notes 1. Typical values at VCC = 3.3 V. 2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. AC WAVEFORMS propagation delay nA, nB to nY skew see Figs 5 and 6 note 2 1.0 - 2.1 - 4.3 1.0 1.0 - 5.5 1.5 ns ns
handbook, halfpage
nA, nB input
VM
tPHL
tPLH
nY output
VM
MNA213
VM = 1.5 V at VCC 2.7 V; VM = 0.5 VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 The input nA, nB to output nY propagation delays.
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 500 VO RL 500
2 x VCC open GND
MNA368
VCC 1.2 V 2.7 V 3.0 to 3.6 V
VI VCC 2.7 V 2.7 V
tPLH/tPHL open open open
Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance (see Chapter "AC characteristics"). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm
74LVC00A
SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 A1 pin 1 index Lp 1 e bp 7 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.050 0.041 0.228 0.016
0.028 0.004 0.012
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
2002 Mar 05
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A X
c y HE vM A
Z 14 8
Q A2 pin 1 index Lp L 1 bp 7 wM detail X A1 (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 EIAJ EUROPEAN PROJECTION
ISSUE DATE 96-01-18 99-12-27
2002 Mar 05
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-04-04 99-12-27
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
74LVC00A
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
Suitability of surface mount IC packages for wave and reflow soldering methods
74LVC00A
SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
74LVC00A
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors
Product specification
Quad 2-input NAND gate
NOTES
74LVC00A
2002 Mar 05
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/03/pp16
Date of release: 2002
Mar 05
Document order number:
9397 750 09442

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